This invention relates to integrated circuit memories. More particularly, this invention relates to the precharging of digit lines in dynamic random access memories (DRAMs).
A DRAM is a form of semiconductor random access memory (RAM) commonly used as main memory in computers and other electronic systems. DRAMs store information in arrays of integrated circuit “cells.” Information is typically read from and written to these cells using pairs of wires called digit lines.
Each DRAM cell has a capacitor to store a logical bit value and is typically accessed with a single pair of digit lines, referred to herein as DL and /DL. When performing a read operation, DL and /DL are precharged to a certain voltage level. For instance, DL and /DL may be precharged to approximately half the power supply voltage (Vcc/2). Precharging can also be referred to as equalization, because the digit line voltages are pulled to substantially equal levels. One of the digit lines, for example DL, is then connected to a voltage stored by the cell's capacitor. This voltage will be higher or lower than the precharge voltage level, depending upon the value of the data stored in the cell. This cell's voltage will pull the voltage of DL upwards or downwards, again depending on the stored value.
At this point, a sense amplifier circuit may be activated in order to amplify the voltage difference between DL and /DL, resulting in a full rail-to-rail voltage difference. For example, a logical 1 may be indicated by a final DL voltage of approximately Vcc and a final /DL voltage of approximately 0V, or ground (GND). The new voltage level at DL can be used to refresh the contents of the memory cell. Thus, precharging is important not only for read operations, but also for routine refresh operations.
In some implementations, the precharge voltage level may differ significantly from Vcc/2. For instance, the precharge voltage level may be about Vcc/2-0.2V. Several techniques have been developed to handle such different precharge levels. However, most known techniques have shortcomings. For instance, the use of a known bleeder gate to connect a digit line pair to the desired precharge voltage may result in a relatively slow voltage change. Or, use of known dual stage precharge techniques may rely on precise timing adjustments, which are based at least partly on circuit simulation results. This reliance on simulation timing tends to create a less robust design.
In view of the foregoing, it would be desirable to provide circuitry and methods that can efficiently precharge digit lines to a level different than Vcc/2, while avoiding reliance on precise timing adjustments.